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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT652 Octal bus transceiver/register; 3-state Product specification File under Integrated Circuits, IC06 September 1993 Philips Semiconductors Product specification Octal bus transceiver/register; 3-state FEATURES * Multiplexed real-time and stored data * Independent register for A and B buses * Independent enables for A and B buses * 3-state * Output capability: Bus driver * Low power consumption by CMOS technology * ICC category: MSI. APPLICATIONS * Bus interfaces. DESCRIPTION The 74HC/HCT652 are high-speed SI-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with Jedec standard no. 7A. The 74HC/HCT652 consist of 8 non-inverting bus transceiver circuits with 3-state outputs, D-type flip-flops and central circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Data on the "A" or "B" or both buses, will be stored in the internal registers, at the appropriate clock pins (CPAB or CPBA) regardless of the select pins (SAB and SBA) or output enable (OEAB and OEBA) control pins. Depending on the select inputs SAB and SBA data can directly go from input to output (real time mode) or data can be controlled by the clock (storage mode), this is when the output enable pins this operating mode permits. The output enable pins OEAB and OEBA determine the operation mode of the transceiver. When OEAB is LOW, no data transmission from An to Bn is 74HC/HCT652 possible and when OEBA is HIGH, there is no data transmission from Bn to An possible. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each output reinforces its input. Thus when all other data sources to the two sets of bus lines are at high-impedance, each set of the bus lines will remain at its last state. This type differs from the HC/HCT646 in one extra bus-management function. This is the possibility to transfer stored "A data to the "B" bus and transfer stored "B" data to the "A" bus at the same time. The examples at the application information demonstrate all bus management functions. Schmitt-trigger action in the clock inputs makes the circuit highly tolerant to slower clock rise and fall times. QUICK REFERENCE DATA GND = 0 V; Tamb = 25C; tr = tf = 6 ns; VCC = 4.5 V; CL = 50 pF. TYPICAL SYMBOL tPLH/tPZL PARAMETER propagation delay An/Bn to Bn /An propagation delay CPAB/CPBA to Bn /An propagation delay SAB/SBA to Bn /An tPHZ/tPZL tPHZ/tPLZ fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL x VCC2 x fo) = sum of the outputs 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V September 1993 2 3-state output enable time OEAB/OEBA to Bn/An 3-state output disable time OEAB/OEBA to Bn/An maximum clock frequency input capacitance power dissipation capacitance per channel notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 13 18 20 14 12 92 3.5 26 HCT 13 20 23 15 13 92 3.5 28 ns ns ns ns ns MHz pF pF UNIT Philips Semiconductors Product specification Octal bus transceiver/register; 3-state ORDERING AND PACKAGE INFORMATION PACKAGE TYPE NUMBER PINS 74HC/HCT652N 74HC/HCT652D PINNING SYMBOL CPAB SAB OEAB A0..A7 GND B7..B0 OEBA SBA CPBA VCC PIN 1 2 3 4..11 12 13..20 21 22 23 24 DESCRIPTION A to B clock input select A to B source input output enable A to B input A data inputs/outputs ground (0 V) B data inputs/outputs output enable B to A input select B to A source input B to A clock input positive supply voltage 24 24 DIL SO PIN POSITION plastic plastic MATERIAL 74HC/HCT652 CODE SOT101L SOT137A Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. September 1993 3 Philips Semiconductors Product specification Octal bus transceiver/register; 3-state FUNCTION TABLE INPUTS (1) OEAB L L X H L L L L H H H Notes 1. H = HIGH voltage level L = LOW voltage level X = don't care = LOW-to-HIGH transition OEBA H H H H X L L L H H L CPAB H or L X X X H or L CPBA H or L X H or L X X SAB X X X L X X X X L H H SBA X X X X X L L H X X H DATA I/O (2) A1 THRU A8 Input Input Input Not specified Ouput Ouput Input Output B1 THRU B8 Input Not specified Output Input Input Input Output Output Isolation 74HC/HCT652 OPERATION OR FUNCTION HC/HCT652 Store A and B data Store A, Hold B Store A in both registers Hold A, Store B Store B in both registers Real Time B Data to A Bus Stored B Data to A Bus Real Time A Data to B Bus Stored A Data to B Bus Stored A Data to B Bus and Stored B Data to A Bus H or L H or L H or L H or L 2. The data output functions may be enabled or disabled by various signals at OEAB and OEBA inputs. Data input functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock inputs. Fig.4 Functional diagram. September 1993 4 Philips Semiconductors Product specification Octal bus transceiver/register; 3-state 74HC/HCT652 Fig.5 Logic diagram. September 1993 5 Philips Semiconductors Product specification Octal bus transceiver/register; 3-state DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI. AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb (C) 74HC SYMBOL PARAMETER +25 - - - - - - - - - - - - - - - - - - 80 16 14 100 20 17 25 5 4 6.0 30 35 -40 to +85 - - - - - - - - - - - - - - - - - - 100 20 17 125 25 21 30 6 5 4.8 24 28 -40 to +125 MAX. 205 41 35 285 57 48 295 59 50 225 45 38 225 45 38 90 18 15 - - - - - - - - - - - - ns - - - - - - - - - - - - - - - - - - 120 24 20 150 30 26 35 7 6 4.0 20 24 74HC/HCT652 TEST CONDITIONS UNIT V CC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6 MIN. TYP. MAX. MIN. MAX. MIN. tPHL/tPLH propagation delay An, Bn to Bn, An propagation delay CPAB, CPBA to Bn, An propagation delay SAB, SBA to Bn, An 3-state output enable time OEAB, OEBA to An, Bn 3-state output disable time OEAB, OEBA to An, Bn output transition time 44 16 13 61 22 18 63 23 18 47 17 14 41 15 12 14 5 4 17 6 5 17 6 5 -8 -3 -2 16 83 98 135 27 23 190 38 32 195 39 33 150 30 26 150 30 26 60 12 10 - - - - - - - - - - - - 170 34 29 240 48 41 245 49 42 190 38 33 190 38 33 75 15 13 - - - - - - - - - - - - tPHL/tPLH ns Fig.7 tPHL/tPLH ns Fig.8 tPZH/tPZL ns Fig.9 tPHZ/tPLZ ns Fig.9 tTHL/tTLH ns Figs 6, 8 tW clock pulse width HIGH or LOW CPAB or CPBA set-up time An, Bn to CPAB, CPBA hold time An, Bn to CPAB, CPBA maximum clock pulse frequency ns Fig.7 tsu ns Fig.7 th ns Fig.7 fmax MHz Fig.7 September 1993 6 Philips Semiconductors Product specification Octal bus transceiver/register; 3-state DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI. 74HC/HCT652 Note to the HCT types The value of additional quiescent supply current (ICC) for unit a load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below INPUT SAB, SBA A0 to A7 and B0 to B7 CPAB, CPBA OEAB OEBA UNIT LOAD COEFFICIENT 0.75 0.75 1.50 1.50 1.50 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb (C) INPUT PARAMETER +25 -40 to +85 TEST CONDITIONS -40 to +125 UNIT V CC WAVEFORMS (V) MIN. TYP. MAX. MIN. MAX. MIN. MAX. - - - - 16 23 27 18 27 39 46 33 - - - - 34 49 55 41 - - - - 41 59 66 50 ns ns ns ns 4.5 4.5 4.5 4.5 Fig.6 Fig.7 Fig.8 Fig.9 tPHL/tPLH tPHL/tPLH tPHL/tPLH tPZH/tPZL propagation delay An, Bn to Bn, An propagation delay CPAB, CPBA to Bn, An propagation delay SAB, SBA to Bn, An 3-state output enable time OEAB, OEBA to An, Bn 3-state output disable time OEAB, OEBA to An, Bn output transition time clock pulse width HIGH or LOW CPAB or CPBA set-up time An, Bn to CPAB, CPBA hold time An, Bn to CPAB, CPBA maximum clock pulse frequency tPHZ/tPLZ - 16 35 - 44 - 53 ns 4.5 Fig.9 tTHL/tTLH tW - 16 5 6 12 - - 20 15 - - 24 18 - ns ns 4.5 4.5 Fig.6, 8 Fig.7 tsu th fmax 10 5 30 5 -2 83 - - - 13 6 24 - - - 15 8 20 - - - ns ns MHz 4.5 4.5 4.5 Fig.7 Fig.7 Fig.7 September 1993 7 Philips Semiconductors Product specification Octal bus transceiver/register; 3-state 74HC/HCT652 (1) HC: VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC: VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Fig.6 Waveforms showing the input An, Bn to output Bn, An propagation delay times and the output transition times. Waveforms showing the An, Bn to CPAB, CPBA set-up and hold times, clock CPAB, CPBA pulse width, maximum clock pulse frequency and the CPAB, CPBA to output Bn, An propagation delays. (1) HC: VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC: VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.9 Fig.8 Waveforms showing the input SAB, SBA to output Bn, An propagation delay times and the output transition times. Waveforms showing the output enable inputs (OEAB, OEBA) to outputs An, Bn enable and disable times and the input rise and fall times. September 1993 8 Philips Semiconductors Product specification Octal bus transceiver/register; 3-state APPLICATION INFORMATION 74HC/HCT652 Fig.10 Application information. September 1993 9 Philips Semiconductors Product specification Octal bus transceiver/register; 3-state PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". 74HC/HCT652 September 1993 10 |
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